EXPLACE
  • List of Exhibitors CHIPEX2016

    TSMC

    UMC

    SYNOPSYS

    CEVA

    INTEL

    Mentor Graphics

    ARM

    Magillem

    Avnet Asic Israel

    Methodics

    SATRIS GROUP

    GUC

    ESTRONICS

    Dini Group

    ST micro

    Design and Reuse

    Faraday Tech

    OneSpin Solutions

    Imagination

    Primetech Semiconductor Products

    Altis Semi Conductor

    Inomize

    On Semiconductor

    RACHIP

    X-FAB Silicon Foundries

    Veriest Solution

    Tower Jazz

    Phoenix Technologies Ltd.

    eSilicon corporation

    Dashro Trade

    Meyer Burger

    NTlab

    Open-Silicon

    NetSpeed Systems

    DeFacto Technologies

    Globalfoundries

    UTAC

    Pro Design

    Qualtera

    S3 Group

    ANSYS Inc

    Silicon Creations

    Vtool

    Secure-ic

    Beyond Electronics

    Cadence Design Systems

    Optima Design Automation

    Milandr

    UniPHY

    UltraSoC

    SmartDV

    vSync Circuits

    eASIC

    Magwel

Sponsors

 
 

  

 

 

  

  

 
 

   

Call for paper - ChipEx2017

Call for Paper – ChipEx2017

ChipEx2017 is the major annual event of the Israeli microelectronics industry.

ChipEx2017 invites any person or company involved with the microelectronics industry

to submit a paper addressing a specific problem or a case study related to the process of microelectronics design, development, implementation and manufacturing.

FYI: The best paper presented at ChipEx2017 will receive a prize of 1,000 NIS!

Submissions must be made via e-mail: info@chiportal.co.il by March 19, 2017 no later than 7:00pm Israel time. Authors of accepted papers will be invited to present their topic at ChipEx2017, scheduled for May 10, 2017 in Tel Aviv, Israel.

Topics of Interest

ChipEx2017 seeks papers addressing one of the following topics:

·         Silicon solutions optimized for the next generation of application (e.g. automotive, high- performance systems, IoT, etc.)

·         Power Management & Signal Integrity

·         Analog Design, RF and Sensors

·         Physical Design and manufacturability

·         Intellectual Property for SoC & NoC

·         Verification, Simulation and Testing

·         Post Silicon and Reliability (including HW testing and packaging)

·         Emerging and creative design technologies

·         Users Track bringing user experience to the public

The main topic of ChipEx2017 is "New tools for new chip design challenges”. Papers that specifically refer to this topic will be treated with higher priority.

 

The following is the process for any paper submission.

  1. The paper should only address one of the selected topics (see below a detailed list of interesting topics). 

2.      Each paper must include an abstract of approximately 50 -100 words clearly stating the impact/result or significant contribution of the submitted topic.

3.      The entire paper should not be longer than two pages (including the abstract)

4.      The author must be ready to present the topic at ChipEx2017. The author or his/her representative will have ~ 20 minutes to present the paper.

5.      Presentations should not be biased or focused towards the author's company or business interests.

6.      Papers which were previously published or simultaneously under review by another conference will be rejected, unless received special authorization by the organizers of ChipEx2017.

7.      Authors of accepted papers must sign a "copyright release form".

 

Submissions not complying with these terms will be rejected.

 

List of interesting topics 

Papers should be submitted only in one of the following categories:

Silicon solutions optimized for the next generation of application (e.g. automotive, high- performance systems, IoT, etc.)

·         IOT devices and applications

·         New processing solution for big data applications

·         Multi-cores and networks-on-chip architectures

·         Cyber aware SoCs and cores

·         Hardware solutions for Cyber security 

·         Innovative solutions for Biomedical applications

·         High- performance systems

·         Configurable and reconfigurable computing

·         Architecture for Embedded System

·         Real time operating systems and middleware

·         Embedded and Flash memories

·         Many and multi-core embedded architecture

·         Software architectures and software engineering

·         Software for Multicore, GPU and novel embedded architecture

·         Custom storage and custom communication design

 

Power Management & Signal Integrity

·         Power/area/performance trade-offs

·         Architectural low power techniques

·         Device and circuit techniques for low power design

·         High level power estimation and optimization

·         Gate level power analysis and optimization

·         System level power design

·         Power analysis and Low Power design

·         Power aware and energy-efficient design for mobile applications

·         New technologies for environmental friendly applications

·         Innovative ways for heat distribution and power management

Analog Design, RF and Sensors

·         Challenges of  Analog, mixed-signal, and RF design

·         MEMS, sensors, actuators, imaging devices 

·         The new era of sensors

·         Analog Front End (AFE) for Sensor Designs

·         Analog baseband circuitry including filters and modulators 

·         Design of heterogeneous distributed embedded systems including wireless sensor networks

·         Nonvolatile devices (e.g. Memristors)

·         I/O management including device drivers, timers, customized interface & communications protocols

·         MEMs applications and usage

Physical Design and manufacturability

·         Design for manufacturability - yield, defect tolerance, and cost impacts

·         The new generation of chip design: 3D integrated circuits

·         Advantages and disadvantages of using 3D design methods (including 2.5D)

·         Suitable application for Silicon Germanium

·         Automated synthesis and clock networks

·         Floor planning, Partitioning, placement buffer insertion, routing, interconnect planning

·         OPC emulation for accurate parasitic extraction

·         FPGA to ASIC path: if, why & what does it take

Intellectual Property for SoC & NoC

·         IP implementation & Reuse

·         IP and platform based design

·         IP Security and protection

·         IP Integration and system configurability

·         IP platforms and Network on Chip

·         IP management while utilizing cloud computing

·         Ensuring compatibility between software drivers and the core IP

·         Increasing the value proposition of third-party hard IPs

·         NoC design methodologies and case studies

·         System level communication and network on chip

Verification, Simulation and Testing

·         Verification plan of HW design and implementation

·         Formal verification & System validation

·         Dynamic simulation, equivalence checking, formal (and semiformal) verification model and property checking

·         Emulation & HW simulators or accelerator engines

·         Functional, transaction-level, RTL and gate level modeling

·         Modeling language and related formalisms

·         Assertion-based verification, coverage analysis, and random test bench generation

·         Simulation and validation of IC design

·         Extraction method for high level simulation

·         Physical verification and design rule checking   

·         Automatic test generation, fault simulation and digital fault modeling

·         Test quality/reliability, current based test and delay test

·         Board and system-level test, system-on-chip (SOC) testing

·         Memory test and repair, FPGA testing, fault-tolerance and online testing

·         Analog/mixed-signal/RF testing, system-in-packages (SIP) testing

·         Test for digital design, test data compression, built-in self test

·         Test for variability, reliability and defects

·         Simulation methods for challenging engineering problems

Post Silicon and Reliability (including HW testing and packaging)

·         Ways to cope with the new manufacturing challenges & costs   

·         Design techniques for System- in-package and package board

·         Automatic Eco flow

·         Packaging issues

·         Silicon debug and diagnosis, post-silicon design validation

·         Rapid prototyping techniques

·         Tests for Reliability

 

Emerging and creative design technologies

·         Using machine learning for better chip design

·         New transistor structures, devices and novel process technologies

·         Alternatives material to silicon – graphene, etc.

·         New optical devices and communication solutions

·         Special geometries for special devices

·         Nanowires, Nanotubes and other Nanotechnologies

·         Quantum computing

·         Emerging Technologies solutions (including better energy management, improved memory utilization, etc.)

·         Biologically- based or biologically-inspired computing systems

·         Cyber-physical systems

·         Reuse methodologies

·         Efficient ways of using Very High Speed interfaces

·         Holistic ways to manage the entire design including Silicon – Package   - and PC Board

·         Ways for securing design data and avoiding unauthorized usage of software and code

Users Trackbringing user experience to the public

We welcome any user that could share with ChipEx2017 audience his/her experience with new tools and/or innovative design methods.

 

 

 

  Call for Paper – ChipEx2017
Jump to page content